Principal Engineer, Power and Signal Integrity:
- Put in place and executed on multi die package extraction, modeling, analysis PDN PI centric flows with Sigrity suite of tools (e.g., XtractIM) and Voltus for digital die + package power & IR drop analysis.
- Spectre ac impedance sweeps comparing full fidelity extracted package model versus reduced order models coming from hybrid solver.
- Singerly developed and deployed modern dashboard for publication to management and team of regular IR drop full chip (and package) or block level runs over various design drops, PVT corners, static, vector-less dynamic, vector driven or combination of simulation approaches.
- Performed all the full chip (TSMC 16nm node) IR drop sweeps (including exhaustive flow tuning, validation, experimentation, documentation, etc.)
2018 to April 2020 ANSYS
Semiconductor Business Unit
Technical Fellow contributing to two main areas of software architecture and development:
Voltage variation and its impact to timing.
- Helping with the integration of ClkDA technologies (amber, clkfx, pathfx) into redhawk-sc for synergistic approach to timing and voltage variation modeling and analysis.
- Specifically wrote code (python) to do distributed or parallel parsing of massive internal timing information along with other vendor's path reports for pre/post voltage drop analysis.
- Various analytics to help user better understand variability of statistical analysis, etc.
Analytics for analysis of large-scale distributed EMIR Drop/Power Data.
- Incorporated a number of open source technologies in Redhawk SeaScape distributed architecture to enable platform independent analytics. For example, twisted python server running on top of SeaScape enabling a highly responsive backend via HTTP protocols.
- Solely developed the dashboard like interface with comprehensive summary of power, static/dynamic IR, electromigration, quality of inputs, analysis results, metrics, etc. in completely asynchronous non-blocking and thus responsive manor (promises).
- Small and light wrapper around DOM objects for much more concise lower level programming API via metaprogramming with proxies, etc.
- Incorporation of D3.js and SlickGrid.js to afford canned interactive analytics with cross probing between tabular data and various graphs, etc. for example, heatmaps, parallel coordinates, scatter plots, etc.
Principal Engineer with focus on global 3-4GHz clock delivery for CPU core (joint venture between AMD and HIGON). Responsibilities and deliverables singularly and solely include but not limited to:
- Global clock modeling and analysis. Working on global clocking to ensure licensed SOC CPU core clocking meets or exceeds design specs despite changes to portions of the design (e.g., floating point unit).
- Solely and singularly responsible for global clocking flow, from building (Cadence Innovus), extraction (StarRC, LEF/DEF, OASIS), simulation (HSPICE/Finesim) and back annotation into STA (SPICE transients to SDC's).
- Wrote code to extract all paths from PT data base across all corners/modes to ensure global clocking skew in areas not redone were not negatively impacted by portion of CPU which was redesigned.
- Test chip clocking delivery design, modeling, analysis and initial implementation in ICC2.
- Brought up parameterized multi-ported, coupled wire load (RLCK) models for SPICE simulation (multi-corner, multi-colored, for clocking, SSB, repeater sweeps, etc.)
- Singularly and solely responsible for CPU and GPU global clock design (include tool development to enable rapid exploration of clock topologies, flow, etc.), modeling (e.g., engineering decap), analysis, and implementation.
- Other activities to help team include but not limited to:
- Initial ownership of top-level floorplan (Innovus) flow build pipe cleaning and delivery.
- Review and input of EMIR flows, Extraction setup/flow (StarRC), fielding cell library questions, etc.
- Wrote OASIS to DEF utility as stop gap measure to be able to create initial floorplan prior to delivery of LEF/DEF from supplier (initial DB consisted only on OASIS DB) - enabled earlier start of design work.
- Training and mentoring of engineers related to various topics, e.g., clocking, design automation, etc.
Programmable Solutions Group
Design, modeling, analysis of global synchronizing clock distribution that resulted
in the elimination of the need for duty cycle correction and dual phase signal
distribution from previous and suggested architecture. Clearly showed the
robustness of a simpler solution via corner and statistical HSPICE sweeps for Intel
14nm CMOS process, etc. Established integration/implementation guidelines for PD
Brought up methodology for SRAM (CRAM) array validation using Synopsys esp-cv. Pipe
cleaned flow on largest of blocks and other challenging circuits (e.g., pulse
generator), documented, make file flows, custom esp-cv test benches (symbolic
simulator/formal equivalency), app notes and compiled internal training/labs.
Wrote ROBDD based (C++, Boost, BuDDY, Si2 Liberty Parser, etc.) utility for
formally validating conditional timing arc conditions for the 64 bit input/6 select
LUT of the next generation high end Stratix FPGA design.
Ensured crowbar mitigating level shifters performed as specified, investigated
other circuit areas of concern w.r.t. same.
2011 to 2014 Oracle
Consulting Hardware Engineer soley responsible for power distribution design, modeling, and analysis.
- Solely responsible for APL characterization of logic, compiled memories (test bench generation/XA simulation, gds2rh/sim2iprof/aplchar, etc.), and other IP w/validation of same.
Solely responsible for power gating switch selection (header vs. footer), sizing, and spactial topology guidelines. Characterization of same.
Decap investigation, e.g., frequency response to neighboring cells vs. leakage ROI, etc.
Initial bump out layout along with RDL and MTOP down to M2 design for PDN.
Investigation into 1st/2nd droop from VR to SOC. Rampup simulations for on die power gated regions. EMIR redhawk flow development for block integrators
Principally responsible for competitive technical assessment and selection of standard cell libraries,
I/O's, and memory compilers.
Investigation/correlation into vendors flop setup/hold/clk2q characterization approach,
i.e., independent setup vs. hold measurements or dependent, clk2q at certain push out or...
Investigation into vendors leakage characterization, e.g., loading/driving of DUT, problematic
".measure pwr" of subckt vs. summation of pins, etc.
Cell by cell tp[lh][hl], t[rf]o, etc., vendors comparison per cell function/drive strength statistics
coupled with real world synthesis/APR results.
Wrote leakage calculator for Architecture/RTL team.
Wrote delay calculator for structured custom methodology.
Wireless Computing Division
Senior Member of Technical Staff responsible for Apache modeling and analysis of dual core
ARM Cortex-A15 (OMAP 5430) processor core. Static and Dynamic IR drop modeling and analysis
looking at the results of:
- Assess PDN robustness of pre/post opportunistic PDN strapping.
- Pre/Post opportunistic decap fill
- Header switch sizing, placement, etc.
- Impact of constraining total block power over multiple power domains
- APL versus CCS .lib power modeling assesment/impact to QOR.
- Wrote (in C++) VCD parser/processor to report out hierarchically AF, scale timings, etc.
- Wrote delay and power calculator (based off of Open Source Liberty Parser) for a number of uses, e.g.,
- Dynamically generated standard cell web documentation so structured custom designers could
become familiar with library characteristics faster (e.g., power/performance/area), quickly
- Identify changes in new library release, etc.
- Validate RedHawk results for complex static scenarios (e.g., memories - read/write activities)
2008 to 2010 NVIDIA Corporation
Involved in various CAD activities, e.g., static timing, post layout timing
optimization, CCS modeling, SI constraints management, etc.
Miscellaneous PCB CAD software development on Windows utilizing Visual Studio C++ with Qt for GUI, Xerces, Boost, and STL libraries.
Technical Lead for physical design (PD) and global clock distribution on 65nm SOI, 9LM, low power, multi-GHz 64bit PowerPC core.
- Solely and singularly responsible for global clock
distribution circuit design (from muxed PLL
output to c1/c2 clock generator inputs).
- Designed, modeled, analysis for low power targets,
aggressive skew control, insensitivity to [FB]EOL variation, mitigation techniques for SOI history impact to duty cycle
distortion, EM and IRMS, etc.
- Wrote utility (30K+ lines of code) to allow for rapid
of aggressive low
power, high performance clock topologies. For example, trees, trees
driving spines, trees with selective shorting
driving meshes/grids, etc. Written on top of floorplanner but interfacing directly to fast spice simulator and device level
statistical analysis package. Accurate (e.g., RLC) but early modeling
allowed for fast exploration and support of "what if" floorplanning changes and improving my own productivity and ability to deliver a global
clock distribution that exceeded initial design goals.
- Enhanced brute force Monte Carlo routines around our
spice simulator to take advantage of computing farm reducing the
statistical simulation of FEOL, BEOL, power supply, etc. on clock
distribution from weeks to hours.
- Pioneered Latin Hypercube sampling approach
statistical analysis on entire clock distribution.
- Work resulted in global clock distribution (output of
PLL/MUX to input of local clock regenerators) having mean skew of under
25ps and mean average power dissipation of
less then 1/2 Watt.
Floorplanning, placement, routing, and integration
- Meeting chair/facilitator for weekly integration/PD
technical and resource coordination meetings throughout the life of the
- Early in the design, singularly responsible for top
level and unit level floorplanning, place, and
route, and integration methodology and execution. Drive methodology
improvements and floorplanning goals through
weekly technical working meetings, etc.
- Performed repeater studies (along w/routability experiments) to ascertain optimal wire
widths/spaces for default and non-default rules. Goal was to optimize for
performance/power goals while not sacrificing routability.
Outcome of this was also inverter/buffer guidelines for RC dominated
paths (e.g., p/n ratios, sizing, spacing, etc.)
- Wrote utility to place thousands of RC pipelining
flops/latches at top level while being synergistic with our structured
custom data path methodology.
- Created script to synthesis clock gating topology for
1st level of gating. Said utility also handled placement & wiring of
- Wrote over 15k lines of code for various floorplanning enhancements such as PD metrics
generation and tracking, early blockage modeling, netlist cleanup, plotting, RC estimation, physical pin promotion through
hierarchy, improvements to handling polygonal shaped unit boundaries, etc.
- Active contribution to project scheduling and
- Taught several classes to project team in the areas of
advanced scripting for floorplanner, advanced tcl scripting, and NanoRoute best known methods.
Senior Member of Technical Staff and technical lead for full chip PD activities
and methodologies on ARM Core (Cortex-A8) targeted at OMAP 3630 SOC.
Participated in development of DVFS multi-domain power distribution design (interconnect
to header switches).
Responsible for back end EDA technology selection and top down/bottom up rapid design
Performed repeater studies, performed early full core timing methodology for RTL
Jointly responsible for high performance library definition. Director of wireless
enlisted my involvement in trouble shooting timing convergence problems
with ARM9 core and ASIC library used on same. The analysis I did turned up
a half a dozen issues which when resolved decreased WNS by 100MHz.
Project interface to 65nm BEOL technology development. Performed BEOL technology
studies including assessment of performance, power, and area differences
between straight or tapered metal stack.
Defined structured relative placement data path methodology.
Solely developed prelayout schematic pseudo 3D wire
load models for coupled noise and delay studies.
Responsible for project scheduling and staffing for all integration and methodology
Technical lead for full chip PD activities on Tejas microprocessor. Senior Staff Engineer contributing to design and methodology. Wrote over 50k lines of code to enhance productivity of floorplanning team, fill in tools gap, generate design metrics, etc.
Wrote a repeater RC delay calculator used in early floorplanning,
solely responsible for early spice simulations of heuristically optimized
repeater chains in which the fitted simulation data was the basis for the
Participated in project scheduling, resource forecasting, and cross site management and
training activities. Designed and taught floorplanning class for micro-architects.
Facilitated wiring studies by driving wiring working group.
Single project representative for Corporate Strategic Technology Readiness in
ensuring CAD tools for future 90nm seven layer copper technology necessary
to support same.
Single project representative for Corporate Working Group in design reuse.
Chair project PD Work Group.
Senior Engineer and Technical Lead for PD and Timing Integration of a
version of the PowerPC 750 (G3) microprocessor.
Aided in creation of project schedule, resources forecasting (engineers,
technicians, design software, workstations, etc.), methodologies,
Focal point for technical exchanges during acquisition through design of
processor IP from IBM.
Chip Integration/floorplanner, singularly responsible
for translation of IBM's proprietary chip level data (VIM = logic +
physical) into Cadence's Design Planner. Cell sizing, parasitic extraction
for full chip static timing, power bus design, etc.
Perform place and route on synthesized control logic areas of the design
Signal integrity and noise analysis study of our foundry's technology resulting
in publication of circuit design guidelines for avoiding interconnect
Generated parameterized pseudo 3D, 3pi wireload models for
custom circuit cross sections using Raphael.
Solely responsible for circuit redesign of data queues incorporating Radiation
hardened latches. Wrote own verilog test benches
and simulated in mixed mode environment to validate performance (and
Oversaw and drove deliverables for data path bit cell (OTS) and combinatorial
standard cell library design group.
Received Peer Awards. Performance rating consistently "exceeds".
Member of Consulting Staff in Performance Verification Research and Design Group (part of the Custom Integrated Circuits R&D Division).
Involved in the benchmarking of high capacity/high speed circuit simulators (e.g.,
Lucent's EMU2, IBM's PARCH/ACES, Berkeley's SYMPHONY). Captured a low
power adiabatic 32 bit adder for use in the benchmark. Generated stimulus
via stimulus test language. Placed and routed design in silicon ensemble
to create detailed parasitic's for use in the
Worked on a new product that involved performance verification (static timing)
driven extraction. Singularly responsible for integrating Cadence's pearl
static timing tool into said new technology.
Specified technical requirements and drove acceptance for a new product to compete
in the dynamic device level power analysis and interconnect reliability (electromigration and joule heating) and power grid (IR
drop) arena. New product was to be based off of Lucent's internal high
speed high capacity device level simulator (EMU2).
Technical mentor to other developers (e.g., taught class on typical ASIC/semi-custom/custom design techniques).
Advisory Engineer working on 400 series PowerPC embedded microprocessors.
Helped establish the Design Automation infrastructure to augment and facilitate design
team. Responsible for identifying focal areas for improvement, new
capabilities (e.g., formal logic validation, power analysis, etc.) project
schedules and resources.
Responsible for power analysis tools ROI and then bring up of EPIC powermill.
Performed power analysis of chip and sub-units.
Created static timing models in the CFI
Delay Calculator Language (DCL) for standard cells and large macros (CACHE's, GPR's, Adders, etc.) used on
Worked on the PD of a semi-custom sub-micron, five layer metal
CMOS CISC microprocessor for IBM's Large Scale Computing Division.
Technical lead for thirteen PD Engineers.
Responsibilities include establishing, overseeing and taking part in the full chip
placement, wiring and assembly. Put in place data management and library
control of PD data. Worked on the development of schedules.
Performed circuit design of compare/error checking logic functional group in data
path area. Used regular structure layout synthesis program to create
Developed and taught a two day course on advanced UNIX which focused on script
writing using various UNIX utilities to help automate and glue together
the PD process.
Automated much of the chip build and assembly process for both PD and full chip
timing. As at Intel, augmented many of the PD tools and processes.
Senior Engineer working in the PD automation area in the P6 (Pentium Pro) design engineering group.
proprietary PD tools into Cadence Framework and data management
environment. Evaluated Mentor Data Path Explorer for use in the data flow
logic of the P6.
and helped automate/plan data path bus layout for timing. Wrote scripts
and Mainsail (object oriented language) MACRO's to augment layout tasks.
a distributed RC network extraction program. Used said work to investigate
clock skew problems and balancing of clock distribution tree. Worked on
developing solutions for assuring reliability requirements such as DC and
in CAD tool development, design process, and methodology meetings. Hiring
of PD Engineers/Technicians. Helped define and actually taught PD
CAD Engineer working in the layout synthesis group for the Intel's
Microprocessor CAD group. Worked on a proprietary block place and route
tool developing features for Intel's generations of X86 architectures
(386SL, 486DX, Pentium, P6, etc.).
Algorithm development work including process shifting, interactive detailed wire
editing, resistance extraction, design for manufacturability and enhanced floorplanning capabilities.
Responsible for the definition, proposal, planning, scheduling and execution of major
areas of functionality for both the block and standard cell place and
Continual research and development on the partitioning problem. Enhanced and
incorporated the work started while with the ASIC group (see below) into
Intel's design synthesis (from iHDL) to physical
Worked on Intel's dense standard cell place and route tool. Developed a
constrained via minimization module, a post processor to the detailed
channel router that ensured DR clean routing, place and route
functionality for FIB/E-Beam methodology, electromigration analysis, and a module to place arrays
of vias at power rail intersections.
CAD Engineer working in PD Automation group for Intel's Standard/Macro Cell
ASIC Group. Took one complete design from netlist acceptance through to tapeout.
Proposed and developed a prelayout partitioning and
hierarchy editing tool. Implemented the netlist parser with lex/yacc.
Wrote over 25k lines of C code implementing all the data structure
manipulation routines and the
algorithm. Guided and worked on the development of a user
interface that utilized OSF's Motif X window library.
Established methodologies for both 1μm and 1.5μm APR systems. Responsible for training,
documentation, and support of 1.5μm layout system (Silvar-Lisco's CAL-MP).
B.S. in Electrical Engineering, 1986. GPA: 3.38 of 4.0. Completed well over half
the requisite credit hours towards a M.S. degree in Computer Engineering.
Other classes include: Oregon Graduate Institute,
Advanced VLSI Device and Logic Design (EE580). Mesa Community College, C Programming
for Programmers. Numerous internal classes, e.g.,
effective meetings, situational leadership, and management by objectives, etc.
Publications and Presentations
"Improvements and Directions to Solving Challenges in RHSC Big Data & Distributed Computing", 2019 ANSYS TechCon, Canonsburg, PA.
"Technology Demonstration of a Full Stack Enterprise Level Application Targeted for EDA/CAD in VLSI design", 2016 Altera (now part of Intel) Technical Symposium.
"Binary Decision Diagrams – Review and Applications in VLSI Design", 2015 Altera Technical Symposium.
"Power Aware Grided Clock Distributions for High-Performance Designs", 2006 Freescale Low Power Symposium, David Artz, Ross Philip, and Shuangjie Zhou.
"Top Three Issues for Performance Entitlement in 65nm CMOS Process: An Interconnect Perspective", Texas Instruments 2nd Annual Interconnect
Symposium, David Artz, Oct. 2003, Dallas TX.
Radiation Hardened PowerPC Microprocessor", Lockheed Martin Space
Electronics & Communications White Paper, Richard Berger, David Artz, Paul Kapcio. 2000.
"Interconnect Characterization System", 11th Karuizawa Workshop Program., Dr. Mark Basel, Dr. Peter Spink, Dr. Tze-Ting Fang, David Artz,
Dr. Prasanti Uppaluri. Cadence Design Systems. 1998.
"Typical Microprocessor Design Flow Using Cadence Tools" Invited Talk for NCSU
EE Graduate Seminar Series hosted by Dr. Paul Franzon,
Dec 1996, Raleigh NC.
"Typical Physical Design Methodologies in Full Custom Microprocessor Design",
Invited Talk at Cascade Design Automation hosted by, Jan 1995, Redmond WA.
"CAD Tool Requirements For Embedded Low Power Microcontroller Design"
Invited Talk for IBM EDA Organization hosted by Dr. John Darringer, 1995, Poughkeepsie NY
"A Solution to Mapping an ASIC Design Hierarchy into an Efficient Block-Place-and-Route Layout Hierarchy",
IEEE Proceedings 3rd ASIC Conference, September 1990.
"Bonus Device Placement and Routing" Intel Design Technology Application Notes, May/June 1991, Volume 4, Number 3.
"Optimizing Netlist Hierarchy for Layout with NETPAR" Intel Design Technology Application Notes, March/April 1991, Volume 4, Number 2.